The present invention relates to the field of electronic data processing and electronic design automation (EDA). More specifically, the present invention is related to EDA tools and methodologies associated with design of systems on chip (SOC), and their verification.
Continued advances in integrated circuit (IC) technology have brought about a tremendous increase in useable space on an IC. In order to fully utilize this space, while keeping costs down, the required per capita output for a given designer on a design team has increased dramatically. As designers"" output progressed from the 10s of gates per day in the 1980s to the 100s of gates per day in the 1990s, several technologies such as synthesis facilitated this growth in productivity. By designing at a hardware description language level instead of a gate level, designers were able to increase productivity to maintain utilization of the increase in available gate capacity.
FIG. 1 shows a typical prior art high-level design process for integrated circuit design. The architecture of an Application Specific Integrated Circuit (ASIC) 110 is determined. From this architecture, a Register Transfer Level (RTL) 120 module of the design is developed. Concurrent with the RTL design, test vectors 130 are developed from the architecture to provide the designer with the ability to verify the functionality of the RTL model through RTL verification 140.
Advances in IC technology are expected to continue, resulting in further growth in the number of gates includable in an IC. Future designs will grow to require that designers"" productivity to reach the millions of gates per day in the not too distant future. Increasingly, designers are putting an entire system in an IC, known as system on chip or SOC. The concept of re-useable intellectual property (IP) or components has emerged to facilitate designers in designing SOC, using existing IP (components) for the xe2x80x9cstandardxe2x80x9d function blocks (such as the compute core, the system bus, memory and the like). However, while various disjointed design automation tools are available to assist the designers, in general, the design process for designing a SOC has remained a very labor intensive effort, requiring a designer to undertake many of the integration tasks to put together a SOC.
Recently, a number of semiconductor manufacturers, such as Oki Semiconductor of Sunnyvale, Calif., Altera of San Jose, Calif., and ARM of Cambridge, United Kingdom, have introduced or announced the intention to introduce additional tools to further assist designers of SOC. However, it is apparent that the current paradigm for designing a SOC remains insufficient to allow design teams to operate at that required level of productivity for future SOC designs. As a result, an improved, more automated and more efficient SOC design process is desired.
The terms xe2x80x9ccustomizationxe2x80x9d and xe2x80x9cconfigurationxe2x80x9d as used herein are generally interchangeable. Each term may include the conventional meaning of the other, unless the context of the usage dictates otherwise.
The term xe2x80x9cbusxe2x80x9d as used herein refers to a collection of signals that implement a data transfer and/or control protocol, and/or xe2x80x9cwiresxe2x80x9d over which the collection of signals are transferred. These signals may include interrupt signals.
The terms xe2x80x9cmastersxe2x80x9d or xe2x80x9cmaster devicesxe2x80x9d refer to devices connected to a bus that can initiate a data/control operation; and the terms xe2x80x9cslavesxe2x80x9d or xe2x80x9cslave devicesxe2x80x9d refer to devices connected to a bus that can only respond to data/control operations.
The term xe2x80x9cgeneratorxe2x80x9d as used herein refers to a collection of programming instructions that take a collection of design information of a SOC as input, process the design information, and output the design information of the SOC in a transformed and/or expanded state to further the design and/or verification of the design of the SOC.
The terms xe2x80x9cverificationxe2x80x9d and xe2x80x9cdebuggingxe2x80x9d (in the enumerated as well as related forms) as used herein are generally interchangeable. Each term may include the conventional meaning of the other, unless the context of the usage dictates otherwise.